New PDF release: 1076.6-1999 IEEE Standard for VHDL Register Transfer Level

ISBN-10: 0738118192

ISBN-13: 9780738118192

A customary syntax and semantics for VHDL sign in move point (RTL) synthesis is outlined. The subset of IEEE 1076 (VHDL) that's compatible for RTL synthesis is outlined, in addition to the semantics of that subset for the synthesis area.

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Additional info for 1076.6-1999 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

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The vector should have a width that is capable of representing all possible values in the range specified for the integer type definition. The synthesis tool should support integer types and positive, negative, and unconstrained (universal) integers whose bounds lie within the range -2,147,483,648 to +2,147,483,647 inclusive (the range that successfully maps 32-bit twos-complement numbers). Subtypes NATURAL and POSITIVE are supported. 24 Copyright © 2000 IEEE. All rights reserved. 6-1999 NOTE—Integer ranges may be synthesized as if the zero value is included.

5 Concurrent signal assignment statement concurrent_signal_assignment_statement ::= [ label: ] [ postponed ] conditional_signal_assignment | [ label: ] [ postponed ] selected_signal_assignment options ::= [ guarded ] [delay_mechanism] Supported: — Concurrent_signal_assignment_statement Ignored: — Options Not supported: — Reserved words postponed and guarded Copyright © 2000 IEEE. All rights reserved. 6-1999 IEEE STANDARD FOR VHDL Any after clauses shall be ignored. Multiple waveform elements shall not be supported.

Example: architecture ARCH begin C <= B not B "00000000" (others => end ARCH; 52 of ENT is when A(0) = '1' else when A(1) = '1' else when A(2) = '1' and RESET = '1' else ('1')); Copyright © 2000 IEEE. All rights reserved. 2 Selected signal assignments selected_signal_assignment ::= with expression select target <= options selected_waveforms ; selected_waveforms ::= { waveform when choices , } waveform when choices Supported: — — Selected_signal_assignment Selected_waveforms Ignored: — Options Selected signal assignments that satisfy either of the following conditions shall not be supported: a) b) The selected waveforms contain a reference to one or more elements of the target signal.

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1076.6-1999 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

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